Download Udemy - VSD - Physical Design Flow Torrent

Torrent Contents Size: 1.5 GB

Udemy - VSD - Physical Design Flow

▼ show more 47 files

001 Clock Tree Routing And Buffering using H-Tree Algorithm.mp4	MP4	66.5 MB
001 Clock Tree Routing And Buffering using H-Tree Algorithm_en.vtt	VTT	12.9 KB
001 Floor-Planning Steps.mp4	MP4	11.9 MB
001 Floor-Planning Steps_en.vtt	VTT	14.9 KB
001 Introduction to IEEE 1481 - 1999 SPEF format.mp4	MP4	78.6 MB
001 Introduction to IEEE 1481 - 1999 SPEF format_en.vtt	VTT	12.5 KB
001 Introduction to Maze Routing - Lee's Algorithm.mp4	MP4	88.2 MB
001 Introduction to Maze Routing - Lee's Algorithm_en.vtt	VTT	12.4 KB
001 Net-list Binding And Placement.mp4	MP4	46.3 MB
001 Net-list Binding And Placement_en.vtt	VTT	13.2 KB
001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time.mp4	MP4	31.5 MB
001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time_en.vtt	VTT	13.2 KB
001 Utilization Factor And Aspect Ratio.mp4	MP4	8.9 MB
001 Utilization Factor And Aspect Ratio_en.vtt	VTT	12.5 KB
002 Concept Of Pre-Placed Cells.mp4	MP4	8.8 MB
002 Concept Of Pre-Placed Cells_en.vtt	VTT	13.3 KB
002 Crosstalk And Clock Net Shielding.mp4	MP4	59.2 MB
002 Crosstalk And Clock Net Shielding_en.vtt	VTT	13 KB
002 Introduction To Clock Jitter and Uncertainty.mp4	MP4	41 MB
002 Introduction To Clock Jitter and Uncertainty_en.vtt	VTT	10.6 KB
002 Lee's Algorithm Conclusion.mp4	MP4	114.9 MB
002 Lee's Algorithm Conclusion_en.vtt	VTT	14 KB
002 Netlist Binding And Placement Optimization.mp4	MP4	15.2 MB
002 Netlist Binding And Placement Optimization_en.vtt	VTT	13.1 KB
002 Optimize Placement Using Estimated Wire Length And Capacitance.mp4	MP4	91.3 MB
002 Optimize Placement Using Estimated Wire Length And Capacitance_en.vtt	VTT	14.4 KB
002 SPEF Representation of a NET.mp4	MP4	65.8 MB
002 SPEF Representation of a NET_en.vtt	VTT	11.3 KB
003 De-coupling Capacitors.mp4	MP4	11.4 MB
003 De-coupling Capacitors_en.vtt	VTT	13.5 KB
003 Design Rule Check.mp4	MP4	99.5 MB
003 Design Rule Check_en.vtt	VTT	13.7 KB
003 Distributed Resistance And Capacitance Representation in SPEF.mp4	MP4	79 MB
003 Distributed Resistance And Capacitance Representation in SPEF_en.vtt	VTT	14.2 KB
003 Optimize Placement Conitnued.mp4	MP4	86.9 MB
003 Optimize Placement Conitnued_en.vtt	VTT	12.1 KB
003 Placement Timing And Clock Tree Synthesis.mp4	MP4	18.3 MB
003 Placement Timing And Clock Tree Synthesis_en.vtt	VTT	12.7 KB
003 Setup Timing Analysis with Multiple Clocks.mp4	MP4	34.4 MB
003 Setup Timing Analysis with Multiple Clocks_en.vtt	VTT	11.7 KB
003 Static Timing Analysis With Real Clocks.mp4	MP4	47.7 MB
003 Static Timing Analysis With Real Clocks_en.vtt	VTT	15.9 KB
004 Clock Net Shielding.mp4	MP4	14.7 MB
004 Clock Net Shielding_en.vtt	VTT	13.6 KB
004 Hold Timing Analysis Concluded.mp4	MP4	74.5 MB
004 Hold Timing Analysis Concluded_en.vtt	VTT	14.1 KB
004 Multiple Clock Timing Analysis And Introduction To Data Slew Check.mp4	MP4	72.8 MB
004 Multiple Clock Timing Analysis And Introduction To Data Slew Check_en.vtt	VTT	12.5 KB
004 Power Planning.mp4	MP4	12.3 MB
004 Power Planning_en.vtt	VTT	15 KB
004 SPEF Header Description, Physical Design Flow Conclusion and What Next !!.mp4	MP4	41.7 MB
004 SPEF Header Description, Physical Design Flow Conclusion and What Next !!_en.vtt	VTT	11.9 KB
005 Data Slew Check.mp4	MP4	82.8 MB
005 Data Slew Check_en.vtt	VTT	13 KB
005 Multiple Clocks Setup Timing Analysis With Real Clocks.mp4	MP4	58 MB
005 Multiple Clocks Setup Timing Analysis With Real Clocks_en.vtt	VTT	11.4 KB
005 Pin Placement And Logical Cell Placement Blockage.mp4	MP4	46.2 MB
005 Pin Placement And Logical Cell Placement Blockage_en.vtt	VTT	13.6 KB
005 Route - DRC Clean - Parasitics Extraction - Final STA.mp4	MP4	22.2 MB
005 Route - DRC Clean - Parasitics Extraction - Final STA_en.vtt	VTT	12.7 KB
Bonus Resources.txt	TXT	409.6 B
Get Bonus Downloads Here.url	URL	204.8 B

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Udemy - VSD - Physical Design Flow

Torrent Contents Size: 1.5 GB

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